3.17.4 SPARC Options

These `-m' switches are supported on the SPARC:

-mno-app-regs

-mapp-regs

Specify `-mapp-regs' to generate output using the global registers 2 through 4, which the SPARC SVR4 ABI reserves for applications. This is the default.

To be fully SVR4 ABI compliant at the cost of some performance loss, specify `-mno-app-regs'. You should compile libraries and system software with this option.

-mfpu

-mhard-float

Generate output containing floating point instructions. This is the default.

-mno-fpu

-msoft-float

Generate output containing library calls for floating point. Warning: the requisite libraries are not available for all SPARC targets. Normally the facilities of the machine's usual C compiler are used, but this cannot be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation. The embedded targets `sparc-*-aout' and `sparclite-*-*' do provide software floating point support.

`-msoft-float' changes the calling convention in the output file; therefore, it is only useful if you compile all of a program with this option. In particular, you need to compile `libgcc.a', the library that comes with GCC, with `-msoft-float' in order for this to work.

-mhard-quad-float

Generate output containing quad-word (long double) floating point instructions.

-msoft-quad-float

Generate output containing library calls for quad-word (long double) floating point instructions. The functions called are those specified in the SPARC ABI. This is the default.

As of this writing, there are no sparc implementations that have hardware support for the quad-word floating point instructions. They all invoke a trap handler for one of these instructions, and then the trap handler emulates the effect of the instruction. Because of the trap handler overhead, this is much slower than calling the ABI library routines. Thus the `-msoft-quad-float' option is the default.

-mno-epilogue

-mepilogue

With `-mepilogue' (the default), the compiler always emits code for function exit at the end of each function. Any function exit in the middle of the function (such as a return statement in C) will generate a jump to the exit code at the end of the function.

With `-mno-epilogue', the compiler tries to emit exit code inline at every function exit.

-mno-flat

-mflat

With `-mflat', the compiler does not generate save/restore instructions and will use a "flat" or single register window calling convention. This model uses %i7 as the frame pointer and is compatible with the normal register window model. Code from either may be intermixed. The local registers and the input registers (0-5) are still treated as "call saved" registers and will be saved on the stack as necessary.

With `-mno-flat' (the default), the compiler emits save/restore instructions (except for leaf functions) and is the normal mode of operation.

-mno-unaligned-doubles

-munaligned-doubles

Assume that doubles have 8 byte alignment. This is the default.

With `-munaligned-doubles', GCC assumes that doubles have 8 byte alignment only if they are contained in another type, or if they have an absolute address. Otherwise, it assumes they have 4 byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating point code.

-mno-faster-structs

-mfaster-structs

With `-mfaster-structs', the compiler assumes that structures should have 8 byte alignment. This enables the use of pairs of ldd and std instructions for copies in structure assignment, in place of twice as many ld and st pairs. However, the use of this changed alignment directly violates the Sparc ABI. Thus, it's intended only for use on targets where the developer acknowledges that their resulting code will not be directly in line with the rules of the ABI.

-mv8

-msparclite

These two options select variations on the SPARC architecture.

By default (unless specifically configured for the Fujitsu SPARClite), GCC generates code for the v7 variant of the SPARC architecture.

`-mv8' will give you SPARC v8 code. The only difference from v7 code is that the compiler emits the integer multiply and integer divide instructions which exist in SPARC v8 but not in SPARC v7.

`-msparclite' will give you SPARClite code. This adds the integer multiply, integer divide step and scan (ffs) instructions which exist in SPARClite but not in SPARC v7.

These options are deprecated and will be deleted in a future GCC release. They have been replaced with `-mcpu=xxx'.

-mcypress

-msupersparc

These two options select the processor for which the code is optimised.

With `-mcypress' (the default), the compiler optimizes code for the Cypress CY7C602 chip, as used in the SparcStation/SparcServer 3xx series. This is also appropriate for the older SparcStation 1, 2, IPX etc.

With `-msupersparc' the compiler optimizes code for the SuperSparc cpu, as used in the SparcStation 10, 1000 and 2000 series. This flag also enables use of the full SPARC v8 instruction set.

These options are deprecated and will be deleted in a future GCC release. They have been replaced with `-mcpu=xxx'.

-mcpu=cpu_type

Set the instruction set, register set, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are `v7', `cypress', `v8', `supersparc', `sparclite', `hypersparc', `sparclite86x', `f930', `f934', `sparclet', `tsc701', `v9', and `ultrasparc'.

Default instruction scheduling parameters are used for values that select an architecture and not an implementation. These are `v7', `v8', `sparclite', `sparclet', `v9'.

Here is a list of each supported architecture and their supported implementations.

v7: cypress v8: supersparc, hypersparc sparclite: f930, f934, sparclite86x sparclet: tsc701 v9: ultrasparc

-mtune=cpu_type

Set the instruction scheduling parameters for machine type cpu_type, but do not set the instruction set or register set that the option `-mcpu=cpu_type' would.

The same values for `-mcpu=cpu_type' are used for `-mtune=cpu_type', though the only useful values are those that select a particular cpu implementation: `cypress', `supersparc', `hypersparc', `f930', `f934', `sparclite86x', `tsc701', `ultrasparc'.

These `-m' switches are supported in addition to the above on the SPARCLET processor.

-mlittle-endian

Generate code for a processor running in little-endian mode.

-mlive-g0

Treat register %g0 as a normal register. GCC will continue to clobber it as necessary but will not assume it always reads as 0.

-mbroken-saverestore

Generate code that does not use non-trivial forms of the save and restore instructions. Early versions of the SPARCLET processor do not correctly handle save and restore instructions used with arguments. They correctly handle them used without arguments. A save instruction used without arguments increments the current window pointer but does not allocate a new stack frame. It is assumed that the window overflow trap handler will properly handle this case as will interrupt handlers.

These `-m' switches are supported in addition to the above on SPARC V9 processors in 64-bit environments.

-mlittle-endian

Generate code for a processor running in little-endian mode.

-m32

-m64

Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits.

-mcmodel=medlow

Generate code for the Medium/Low code model: the program must be linked in the low 32 bits of the address space. Pointers are 64 bits. Programs can be statically or dynamically linked.

-mcmodel=medmid

Generate code for the Medium/Middle code model: the program must be linked in the low 44 bits of the address space, the text segment must be less than 2G bytes, and data segment must be within 2G of the text segment. Pointers are 64 bits.

-mcmodel=medany

Generate code for the Medium/Anywhere code model: the program may be linked anywhere in the address space, the text segment must be less than 2G bytes, and data segment must be within 2G of the text segment. Pointers are 64 bits.

-mcmodel=embmedany

Generate code for the Medium/Anywhere code model for embedded systems: assume a 32-bit text and a 32-bit data segment, both starting anywhere (determined at link time). Register %g4 points to the base of the data segment. Pointers are still 64 bits. Programs are statically linked, PIC is not supported.

-mstack-bias

-mno-stack-bias

With `-mstack-bias', GCC assumes that the stack pointer, and frame pointer if present, are offset by -2047 which must be added back when making stack frame references. Otherwise, assume no such offset is present.